View CY7B991V-5JCT_1875538.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

low voltage programmabl e skew clock buffer cy7b991v 3.3v roboclock ? cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-07141 rev. *c revised june 20, 2007 features all output pair skew <100 ps typical (250 max) 3.75 to 80 mhz output operation user selectable output functions ? selectable skew to 18 ns ? inverted and non-inverted ? operation at 1 ? 2 and 1 ? 4 input frequency ? operation at 2x and 4x input frequency (input as low as 3.75 mhz) zero input to output delay 50% duty cycle outputs lvttl outputs drive 50 terminated lines operates from a single 3.3v supply low operating current 32-pin plcc package jitter 100 ps (typical) functional description the cy7b991v low voltage programmable skew clock buffer (lvpscb) offers user selectable control over system clock functions. these multiple output clock drivers provide the system integrator with functions necessary to optimize the timing of high-performance computer syst ems. each of the eight individual drivers, arranged in four pairs of user controllable outputs can drive terminated tr ansmission lines with impedances as low as 50 . this delivers minimal and specified output skews and full swing logic levels (lvttl). each output is hardwired to one of nine delay or function config- urations. delay increments of 0.7 to 1.5 ns are determined by the operating frequency with outputs able to skew up to 6 time units from their nominal ?zero? skew position. the completely integrated pll allows external load and transmission line delay effects to be canceled. when th is ?zero delay? capability of the lvpscb is combined with the sele ctable output skew functions, the user can create output-to-ou tput delays of up to 12 time units. divide-by-two and divide-by-four output functions are provided for additional flexibility in designing complex clock systems. when combined with the internal pll, these divide functions enable distribution of a low freque ncy clock that is multiplied by two or four at the clock destinati on. this facility minimizes clock distribution difficulty allowing maximum system clock speed and flexibility. test fb ref vco and time unit generator fs select inputs (three level) skew select matrix 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 filter phase freq det logic block diagram
cy7b991v 3.3v roboclock ? document number: 38-07141 rev. *c page 2 of 14 pin configuration pin definitions signal name io description ref i reference frequency input. this input supplies t he frequency and timing against which all functional variations are measured. fb i pll feedback input (typically conn ected to one of the eight outputs). fs i three level frequency range select. see table 1 . 1f0, 1f1 i three level function select inputs for output pair 1 (1q0, 1q1). see table 2 2f0, 2f1 i three level function select inputs for output pair 2 (2q0, 2q1). see table 2 3f0, 3f1 i three level function select inputs for output pair 3 (3q0, 3q1). see table 2 4f0, 4f1 i three level function select inputs for output pair 4 (4q0, 4q1). see table 2 test i three level select. see test mode se ction under the block diagram descriptions. 1q0, 1q1 o output pair 1. see table 2 2q0, 2q1 o output pair 2. see table 2 3q0, 3q1 o output pair 3. see table 2 4q0, 4q1 o output pair 4. see table 2 v ccn pwr power supply for output drivers. v ccq pwr power supply for internal circuitry. gnd pwr ground. 1 2 3 4323130 17 16 15 14 18 19 20 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 3f0 fs v ref gnd test 2f1 fb 2q1 2q0 ccq 2f0 gnd 1f1 1f0 v ccn 1q0 1q1 gnd gnd 3q1 3q0 ccn v ccn v 3f1 4f0 4f1 ccq v ccn 4q1 4q0 gnd gnd cy7b991v
cy7b991v 3.3v roboclock ? document number: 38-07141 rev. *c page 3 of 14 block diagram description phase frequency detector and filter the phase frequency detector and filter blocks accept inputs from the reference frequency (ref) input and the feedback (fb) input. they generate correction information to control the frequency of the voltage contro lled oscillator (vco). these blocks, along with the vco, form a phase locked loop (pll) that tracks the incoming ref signal. vco and time unit generator the vco accepts analog control inputs from the pll filter block. it generates a frequency that is used by the time unit generator to create discrete time units, se lected in the skew select matrix. the operational range of the vco is determined by the fs control pin. the time unit (t u ) is determined by the operating frequency of the device and the le vel of the fs pin as shown in table 1 . skew select matrix the skew select matrix is comprised of four independent sections. each section has two low skew, high fanout drivers (xq0, xq1), and two corresponding three level function select (xf0, xf1) inputs. ta ble 2 shows the nine possible output functions for each section as determined by the function select inputs. all times are measured with respect to the ref input assuming that the output connected to the fb input has 0t u selected. table 1. frequency range select and t u calculation [ 1 ] fs [2, 3] f nom (mhz) where n = approximate frequency (mhz) at which t u = 1.0 ns min max low 15 30 44 22.7 mid 25 50 26 38.5 high 40 80 16 62.5 t u 1 f nom n ----------------------- - = table 2. programmable skew configurations [1] function selects output functions 1f1, 2f1, 3f1, 4f1 1f0, 2f0, 3f0, 4f0 1q0, 1q1, 2q0, 2q1 3q0, 3q1 4q0, 4q1 low low ?4t u divide by 2 divide by 2 low mid ?3t u ?6t u ?6t u low high ?2t u ?4t u ?4t u mid low ?1t u ?2t u ?2t u mid mid 0t u 0t u 0t u mid high +1t u +2t u +2t u high low +2t u +4t u +4t u high mid +3t u +6t u +6t u high high +4t u divide by 4 inverted notes 1. for all three state inputs, high indicates a connection to v cc , low indicates a connection to gnd, and mid indicates an open connection. internal termination circuitry holds an unconnected input to v cc /2. 2. the level to be set on fs is determined by the ?normal? operating frequency (f nom ) of the v co and time unit generator (see ). nominal frequency (f nom ) always appears at 1q0 and the other outputs when they are operated in their undivided modes (see table 2 ). the frequency appearing at the ref and fb inputs is f nom when the output connected to fb is undivided. the frequency of the ref and fb inputs is f nom /2 or f nom /4 when the part is configured for a frequency multiplication using a divided output as the fb input. 3. when the fs pin is selected high, the ref input must not transition upon power up until v cc has reached 2.8v.
cy7b991v 3.3v roboclock ? document number: 38-07141 rev. *c page 4 of 14 test mode the test input is a three level input. in normal system operation, this pin is conn ected to ground, allowing the cy7b991v to operate as explained in the ?block diagram description? on page 3. for testing purposes, any of the three level inputs can have a removable jumper to ground or be tied low through a 100w resistor. this enables an external tester to change the state of these pins. if the test input is forced to its mid or high state, the device operates with its internal phase locked loop disconnected, and input levels supplied to ref direct ly controls all outputs. relative output to output functions are the same as in normal mode. in contrast with normal operation (test tied low), all outputs function based only on the connection of their own function select inputs (xf0 and xf1) and the waveform characteristics of the ref input. figure 1. typical outputs with fb connected to a zero skew output test mode [4] t 0 ? 6t u t 0 ? 5t u t 0 ? 4t u t 0 ? 3t u t 0 ? 2t u t 0 ? 1t u t 0 t 0 +1t u t 0 t 0 t 0 t 0 t 0 +2t u +3t u +4t u +5t u +6t u fbinput refinput ? 6t u ? 4t u ? 3t u ? 2t u ? 1t u 0t u +1t u +2t u +3t u +4t u +6t u divided invert lm lh (n/a) ml (n/a) mm (n/a) mh (n/a) hl hm ll/hh hh 3fx 4fx (n/a) ll lm lh ml mm mh hl hm hh (n/a) (n/a) (n/a) 1fx 2fx note 4. fb connected to an output selected for ?zero? skew (i.e., xf1 = xf0 = mid).
cy7b991v 3.3v roboclock ? document number: 38-07141 rev. *c page 5 of 14 operational m ode descriptions figure 2 shows the lvpscb configured as a zero skew clock buffer. in this mode, the cy7b991v is the basis for a low skew clock distribution tree. when all of the function select inputs (xf0, xf1) are left open, the outputs are aligned and drive a termina ted transmission line to an independent load. the fb input is tied to any output in this configur ation and the operating frequency range is selected with the fs pin. the low skew specification, coupled with the ability to drive terminated transmission lines (with impedances as low as 50 ohms), enables efficient printed circuit board design. figure 3 shows a configuration to equalize skew between metal traces of different lengths. in addition to low skew between outputs, the lvpscb is programmed to stagger the timing of its outpu ts. the four groups of output pairs are each pr ogrammed to different output timing. skew timing is adjusted over a wide range in sma ll increments with the appropriate strapping of the function sel ect pins. in this configuration, the 4q0 output is sent back to fb and co nfigured for zero skew. the other three pairs of outputs are pro grammed to yield different skews relative to the feedback. by advancing the clock signal on the longer traces or retarding the clock si gnal on shorter traces, all loads receive the clock pulse at the same time. figure 2. zero skew and zero delay clock driver figure 3. programmable skew clock driver system clock l1 l2 l3 l4 length l1 = l2 = l3 = l4 fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 test z 0 load load load load ref z 0 z 0 z 0 length l1 = l2 l3 < l2 by 6 inches l4 > l2 by 6 inches sys- tem clock l1 l2 l3 l4 fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 test z 0 load load load load ref z 0 z 0 z 0
cy7b991v 3.3v roboclock ? document number: 38-07141 rev. *c page 6 of 14 figure 3 shows the fb input connected to an output with 0 ns skew (xf1, xf0 = mid) selected. the inter nal pll synchronizes the fb and ref inputs and aligns their rising edges to make certain that all outputs have precise phase alignment. clock skews are advanced by 6 time units (tu) when using an output selected for zero skew as the feedback. a wider range of delays is possible if the output connected to fb is also skewed. since ?zero skew?, +tu, and ?t u are defined relative to output groups, and the pll aligns the rising edges of ref and fb, wider output skews are created by proper selection of the xfn inputs. for example, a +10 tu between ref and 3qx is achieved by connecting 1q0 to fb and setting 1f0 = 1f1 = gnd, 3f0 = mid, and 3f1 = high. (since fb aligns at ?4 tu, and 3qx skews to +6 tu, a total of +10 tu skew is re alized.) many other configurations are realized by skewing both the outputs used as the fb input and skewing the other outputs. figure 4 shows an example of the in vert function of the lvpscb. in this example the 4q0 output used as the fb input is programmed for invert (4f0 = 4f 1 = high) while the other three pairs of outputs are programmed for zero skew. when 4f0 and 4f1 are tied high, 4q0 and 4q1 become inverted zero phase outputs. the pll aligns the rising edge of the fb input with the rising edge of the ref. this caus es the 1q, 2q, and 3q outputs to become the ?inverted? outputs to the ref input. by selecting the output connected to fb, you can have two inverted and six non-inverted outputs or six inverted and two non-inverted outputs. the correct configuration is determined by the need for more (or fewer) inverted outputs. 1q, 2q, and 3q outputs are also skewed to compensate for varying trace delays independent of inversion on 4q. figure 5 shows the lvpscb configured as a clock multiplier. the 3q0 output is programmed to divide by four and is sent back to fb. this causes the pll to increase its frequency until the 3q0 and 3q1 outputs are locked at 20 mhz, while the 1qx and 2qx outputs run at 80 mhz. the 4q0 and 4q1 outputs are programmed to divide by two that results in a 40 mhz waveform at these outputs. no te that the 20 and 40 mhz clocks fall simul- taneously and are out of phase on their rising edge. this enables the designer to use the rising edges of the 1 ? 2 frequency and 1 ? 4 frequency outputs without concern for rising edge skew. the 2q0, 2q1, 1q0, and 1q1 output s run at 80 mhz and are skewed by programming their select inputs accordingly. note that the fs pin is wired for 80 mhz operation as that is the frequency of the fastest output. figure 6 shows the lvpscb in a cloc k divider application. 2q0 is sent back to the fb input and programmed for zero skew. 3qx is programmed to divide by four. 4qx is programmed to divide by two. note that the falling edges of the 4qx and 3qx outputs are aligned. this enables use of the rising edges of the 1 ? 2 frequency and 1 ? 4 frequency without concern for skew mismatch. the 1qx outputs are programmed to zero skew and are aligned with the 2qx outputs. in this example, the fs input is grounded to configure the device in the 15 to 30 mhz range since the highest frequency output is running at 20 mhz. figure 4. inverted output connections 7b991v?11 fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 test ref figure 5. frequency multiplier with skew connections figure 6. frequency divider connections 7b991v?12 fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 test ref 20 mhz 20 mhz 40 mhz 80 mhz 7b991v?13 fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 test ref 20 mhz 5 mhz 10 mhz 20 mhz
cy7b991v 3.3v roboclock ? document number: 38-07141 rev. *c page 7 of 14 figure 7 shows some of the functions that are selectable on the 3qx and 4qx outputs. these include inverted outputs and outputs that offer divide-by-2 and divide-by-4 timing. an inverted output enables the system designer to clock different subsystems on opposite edges without suffering from the pulse asymmetry typical of non-ideal loading. this function enables each of the two subsystems to clock 180 degrees out of phase, but still is aligned within the skew specification. the divided outputs offer a zero delay divider for portions of the system that divide the clock by ei ther two or four, and still remain within a narrow skew of the ?1x? clock. without this feature, an external divider is added, and the propagation delay of the divider adds to the skew between the different clock signals. these divided outputs, coupled with the phase locked loop, enable the lvpscb to multiply th e clock rate at the ref input by either two or four. this mode allows the designer to distribute a low frequency clock between various portions of the system. it also locally multiplies the clock rate to a more suitable frequency, while still maintaining the low skew characteristics of the clock driver. the lvpscb performs all of the functions described in this section at the same time. it can multiply by two and four or divide by two (and four) at the same time that it shifts its outputs over a wide range or maintains zero skew between selected outputs. . figure 7. multi-function clock driver 20 mhz distribution clock 80 mhz inverted z 0 20 mhz 80 mhz zero skew 80 mhz skewed ?3.125 ns (?4t u ) fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 test ref load load load load z 0 z 0 z 0
cy7b991v 3.3v roboclock ? document number: 38-07141 rev. *c page 8 of 14 figure 8 shows the cy7b991v connected in series to construct a ze ro skew clock distribution tree between boards. delays of the downstream clock buffers are programmed to compensate for the wir e length (that is, select negative skew equal to the wire dela y) necessary to connect them to the master clock source, approximating a zero delay cl ock tree. cascaded clock buffers accumulate low frequency jitter because of the non-ideal filtering characteristics of the pll filter. do not connect more than two clock b uffers in a series. maximum ratings operating outside these boundaries may affect the performance and life of the device. these user guidelines are not tested. storage temperature ................ .............. ... ?65c to +150c ambient temperature with power applied ............ ............... .............. ... ?55c to +125c supply voltage to ground potentia l................?0.5v to +7.0v dc input voltage ............................................?0.5v to +7.0v output current into outputs (low)............................. 64 ma static discharge voltage....... ........... ............ .............. >2001v (mil-std-883, method 3015) latch up current...................................................... >200 ma figure 8. board-to-board clock distribution system clock z 0 l1 l2 l3 l4 fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 test ref 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 ref fs fb load load load load load test z 0 z 0 z 0 operating range range ambient temperature v cc commercial 0c to +70c 3.3v 10% industrial ?40c to +85c 3.3v 10%
cy7b991v 3.3v roboclock ? document number: 38-07141 rev. *c page 9 of 14 electrical characteristics over the operating range [5] parameter description test conditions cy7b991v unit min max v oh output high voltage v cc = min, i oh = ?12 ma 2.4 v v ol output low voltage v cc = min, i ol = 35 ma 0.45 v v ih input high voltage (ref and fb inputs only) 2.0 v cc v v il input low voltage (ref and fb inputs only) ?0.5 0.8 v v ihh three level input high voltage (test, fs, xfn) [6] min v cc max. 0.87 * v cc v cc v v imm three level input mid voltage (test, fs, xfn) [6] min v cc max. 0.47 * v cc 0.53 * v cc v v ill three level input low voltage (test, fs, xfn) [6] min v cc max. 0.0 0.13 * v cc v i ih input high leakage current (ref and fb inputs only) v cc = max, v in = max. 20 a i il input low leakage current (ref and fb inputs only) v cc = max, v in = 0.4v ? 20 a i ihh input high current (test, fs, xfn) v in = v cc 200 a i imm input mid current (test, fs, xfn) v in = v cc /2 ? 50 50 a i ill input low current (test, fs, xfn) v in = gnd ? 200 a i os short circuit current [7] v cc = max v out =gnd (25 only) ?200 ma i ccq operating current used by internal circuitry v ccn = v ccq = max, all input selects open com?l 95 ma mil/ind 100 i ccn output buffer current per output pair [8] v ccn = v ccq = max, i out = 0 ma input selects open, f max 19 ma pd power dissipation per output pair [9] v ccn = v ccq = max, i out = 0 ma input selects open, f max 104 mw ? notes 5. see the last page of this specification for group a subgroup testing information. 6. these inputs are normally wired to v cc , gnd, or left unconnected (actual thresh old voltages vary as a percentage of v cc ). internal termination resistors hold unconnected inputs at v cc /2. if these inputs are switched, the function and timing of the outputs glitch and the pll requires an additional t lock time before all datasheet limits are achieved. 7. cy7b991v is tested one output at a time, output shorted for less than one second, less than 10% duty cycle. room temperature only. 8. total output current per output pair is approximated by the fo llowing expression that includes device current plus load curre nt: cy7b991v: i ccn = [(4 + 0.11f) + [((835 ?3f)/z) + (.0022fc)]n] x 1.1 where f = frequency in mhz c = capacitive load in pf z = line impedance in ohms n = number of loaded outputs; 0, 1, or 2 fc = f < c 9. these inputs are normally wired to v cc , gnd, or left unconnected (actual thresh old voltages vary as a percentage of v cc ). internal termination resistors hold unconnected inputs at v cc /2. if these inputs are switched, the function and timing of the outputs may glitch and the pll may require an additional t lock time before all datasheet limits are achieved.
cy7b991v 3.3v roboclock ? document number: 38-07141 rev. *c page 10 of 14 capacitance tested initially and after any design or proces s changes that may affect these parameters. [10]] parameter description test conditions max unit c in input capacitance t a = 25c, f = 1 mhz, v cc = 3.3v 10 pf ac test loads and waveforms figure 9. test loads and waveforms ttl ac test load ttl input test waveform v cc r1 r2 c l 3.0v 2.0v v th =1.5v 0.8v 0.0v 1 ns 1 ns 2.0v 0.8v v th =1.5v r1=100 r2=100 c l =30pf (includes fixture and probe capacitance) note 10. applies to ref and fb inputs only. tested initially and after any design or process changes that may affect these parameters .
cy7b991v 3.3v roboclock ? document number: 38-07141 rev. *c page 11 of 14 switching characteristics ? 5 option over the operating range [2, 10] parameter description cy7b991v?5 unit min typ max f nom operating clock frequency in mhz fs = low [1, 2] 15 30 mhz fs = mid [1, 2] 25 50 fs = high [1, 2] 40 80 t rpwh ref pulse width high 5.0 ns t rpwl ref pulse width low 5.0 ns t u programmable skew unit see table 1 t skewpr zero output matched-pair skew (xq0, xq1) [14, 15] 0.1 0.25 ns t skew0 zero output skew (all outputs) [[14, 15] 0.25 0.5 ns t skew1 output skew (rise-rise, fall-fall, same class outputs) [14, 18] 0.6 0.7 ns t skew2 output skew (rise-fall, nominal-inverted, divided-divided) [14, 18] 0.5 1.0 ns t skew3 output skew (rise-rise, fall- fall, different class outputs) 14, 18] 0.5 0.7 ns t skew4 output skew (rise-fall, nomi nal-divided, divided-inverted) 14, 18] 0.5 1.0 ns t dev device-to-device skew [13, 19] 1.25 ns t pd propagation delay, ref rise to fb rise ?0.5 0.0 +0.5 ns t odcv output duty cycle variation [20] ?1.0 0.0 +1.0 ns t pwh output high time deviation from 50% [21] 2.5 ns t pwl output low time deviation from 50% [21] 3ns t orise output rise time [21, 22] 0.15 1.0 1.5 ns t ofall output fall time [21, 22] 0.15 1.0 1.5 ns t lock pll lock time [22] 0.5 ms t jr cycle-to-cycle output jitter rms [13] 25 ps peak-to-peak [13] 200 ps notes 11. test measurement levels for the cy7b991v are ttl levels (1.5v to 1.5v). test conditions assume si gnal transition times of 2 ns or less and output loading as shown in the ac test loads and waveforms unless otherwise specified. 12. guaranteed by statistical correlation. tested initially and after any design or process changes that may affect these parame ters. 13. skew is defined as the time between the earliest and the la test output transition among all outputs for which the same t u delay has been selected when all are loaded with 30 pf and terminated with 50 to v cc /2 (cy7b991v). 14. t skewpr is defined as the skew between a pair of outputs (xq0 and xq1) when all eight outputs are selected for 0t u . 15. t skew0 is defined as the skew between outputs when they are selected for 0t u . other outputs are divided or inverted but not shifted. 16. c l =0 pf. for c l =30 pf, t skew0 =0.35 ns. 17. there are three classes of outputs: nominal (multiple of t u delay), inverted (4q0 and 4q1 only with 4f0 = 4f1 = high), and divided (3qx and 4qx only in divide-by-2 or divide-by-4 mode). 18. t dev is the output-to-output skew between any two devices operating under the same conditions (v cc ambient temperature, air flow, etc.) 19. t odcv is the deviation of the output from a 50% duty cycle. output pulse width variations are included in t skew2 and t skew4 specifications. 20. specified with outputs loaded with 30 pf for the cy7b991v?5 and ?7 devices. devices are terminated through 50 to v cc /2.t pwh is measured at 2.0v. t pwl is measured at 0.8v. 21. t orise and t ofall measured between 0.8v and 2.0v. 22. t lock is the time that is required before synchronization is achieved. this specification is valid only after v cc is stable and within normal operating limits. this parameter is measured from the application of a new signal or frequency at ref or fb until t pd is within specified limits.
cy7b991v 3.3v roboclock ? document number: 38-07141 rev. *c page 12 of 14 switching characteristics ? 7 option over the operating range [2, 10] parameter description cy7b991v?7 unit min typ max f nom operating clock frequency in mhz fs = low [1, 2] 15 30 mhz fs = mid [1, 2] 25 50 fs = high [1, 2] 40 80 t rpwh ref pulse width high 5.0 ns t rpwl ref pulse width low 5.0 ns t u programmable skew unit see table 1 t skewpr zero output matched pair skew (xq0, xq1) [14, 15] 0.1 0.25 ns t skew0 zero output skew (all outputs) [14, 16] 0.3 0.75 ns t skew1 output skew (rise-rise, fall-fall, same class outputs) [13, 17] 0.6 1.0 ns t skew2 output skew (rise-fall, nominal-inverted, divided-divided) [14, 18] 1.0 1.5 ns t skew3 output skew (rise-rise, fall- fall, different class outputs) [14, 18] 0.7 1.2 ns t skew4 output skew (rise-fall, nomi nal-divided, divided-inverted) [14, 18] 1.2 1.7 ns t dev device-to-device skew [13, 19] 1.65 ns t pd propagation delay, ref rise to fb rise ?0.7 0.0 +0.7 ns t odcv output duty cycle variation [19] ?1.2 0.0 +1.2 ns t pwh output high time deviation from 50% [20] 3ns t pwl output low time deviation from 50% [20] 3.5 ns t orise output rise time [20, 21] 0.15 1.5 2.5 ns t ofall output fall time [20, 21] 0.15 1.5 2.5 ns t lock pll lock time [22] 0.5 ms t jr cycle-to-cycle output jitter rms [12] 25 ps peak-to-peak [12] 200 ps
cy7b991v 3.3v roboclock ? document number: 38-07141 rev. *c page 13 of 14 ordering information accuracy (ps) ordering code package type operating range 250 cy7b991v?2jc 32-pb plastic leaded chip carrier commercial cy7b991v?2jct 32-pb plastic leaded chip carrier ? tape and reel commercial 500 cy7b991v?5jc 32-pb plastic leaded chip carrier commercial cy7b991v?5jct 32-pb plastic leaded chip carrier ? tape and reel commercial cy7b991v?5ji 32-pb plastic leaded chip carrier industrial cy7b991v?5jit 32-pb plastic leaded chip carrier ? tape and reel industrial 750 cy7b991v?7jc 32-pb plastic leaded chip carrier commercial cy7b991v?7jct 32-pb plastic leaded chip carrier ? tape and reel commercial pb-free 250 cy7b991v?2jxc 32-pb plastic leaded chip carrier commercial cy7b991v?2jxct 32-pb plastic leaded chip carrier ? tape and reel commercial 500 cy7b991v?5jxc 32-pb plastic leaded chip carrier commercial cy7b991v?5jxct 32-pb plastic leaded chip carrier ? tape and reel commercial cy7b991v?5jxi 32-pb plastic leaded chip carrier industrial cy7b991v?5jxit 32-pb plastic leaded chip carrier ? tape and reel industrial 750 cy7b991v?7jxc 32-pb plastic leaded chip carrier commercial cy7b991v?7jxct 32-pb plastic leaded chip carrier ? tape and reel commercial package diagram figure 10. 32-pin plastic leaded chip carrier j65 51-85002-*b
document number: 38-07141 rev. *c revised june 20, 2007 page 14 of 14 psoc designer?, programmable system-on-chip ?, and psoc express? are trademarks and psoc? is a registered trademark of cypress s emiconductor corp. all other trademarks or registered trademarks referenced herein are property of the respective corporations. purchase of i 2 c components from cypress or one of its sublicense d associated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. roboclock is a registered trademark of cypress semiconductor corporation. all products and company names mentioned in this document may be the trademarks of their respective holders. cy7b991v 3.3v roboclock ? document history page document title: cy7b991v 3.3v roboclock ? low voltage programmable skew clock buffer document number: 38-07141 rev. ecn no. issue date orig. of change description of change ** 110250 12/17/01 szv change from spec ification number: 38-00641 to 38-07141 *a 293239 see ecn rgl added pb-free devices added typical value for jitter (peak) *b 1199925 see ecn kvm/aesa format change in ordering in formation table *c 1286064 see ecn aesa change status to final

▲Up To Search▲

Price & Availability of CY7B991V-5JCT

	To Download CY7B991V-5JCT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .